The present invention relates to a semiconductor memory device and a method for reading information from the semiconductor memory device.
Recent dynamic random access memory devices (DRAMs) have higher integration, larger capacity, and less power consumption. Due to the higher integration of memory cell arrays, the memory cells included in the memory cell arrays have become smaller. This leads to a tendency in which the amount of charge accumulates as cell information in cell capacitance of each memory cell decreases.
In such DRAM, power consumption is reduced by prolonging a self-refresh operation or by prolonging an external refresh operation. The DRAM has a dummy word line and a coupling capacitor to read normal cell information based on a small voltage output from a memory cell. The coupling capacitor is located between the dummy word line and a bit line. To read cell information, the dummy word line is selected to increase the voltage of the bit line in accordance with the charge of the capacitor and add the increased voltage to the small voltage read to the bit line. In such DRAM, improved refresh characteristics and higher integration are required.
FIG. 1 is a schematic circuit diagram of a conventional semiconductor memory device (DRAM) provided with a function for complementing cell information with a dummy line.
A cell array 1 includes a plurality (two in FIG. 1) of memory cells 2a, 2b. The memory cell 2a is connected to an intersection between a bit line BL and a word line WL0. The memory cell 2b is connected to an intersection between an inverting bit line /BL and a word line WL1.
The memory cell 2a includes a cell transistor Tr and a cell capacitance C1. The cell transistor Tr includes a first terminal connected to the bit line BL, a second terminal connected to the cell capacitance C1, and a gate connected to the word line WL0. The cell capacitance C1 has a first electrode connected to the cell transistor Tr and a second electrode supplied with a predetermined cell plate voltage. The cell plate voltage is, for example, one half the voltage of a cell power supply ViiC/2, which is supplied to the cell array 1 (hereafter referred to as ViiC/2 and depicted in FIG. 1 as xc2xd ViiC)
A sense amplifier 3 is connected to the bit lines BL, /BL to amplify the cell information read to the bit lines BL, /BL. The sense amplifier 3 receives activation voltages SAP, SAN, which are generated by a sense amplifier voltage generation circuit 4. The sense amplifier voltage generation circuit 4 receives a latch enable signal (sense amplifier activation signal) LE and generates the activation signals SAP, SAN based on the latch enable signal LE. The sense amplifier 3 is activated and inactivated based on the latch enable signal LE.
A dummy cell 5a is connected to an intersection between a bit line BL and a dummy word line DWL0. A dummy cell 5b is connected to an intersection between the inverting bit line /BL and a dummy word line DWL1. The dummy cells 5a, 5b have the same configuration as the memory cell 2a. 
A row address decoder and a word driver (not shown) select one of the word lines WL0, WL1 based on a row address signal. Further, the row address decoder and a dummy word driver (not shown) select one of the dummy word lines DWL0, DWL1.
For example, when the memory cell 2a connected to the bit line BL is selected, the dummy word line DWL0 is selected to increase the voltage of the dummy word line DWL0 from power supply voltage Vss to power supply voltage Vii. When the memory cell 2b connected to the inverting bit line /BL is selected, the dummy word line DWL1 is selected to increase the voltage of the dummy word line DWL1 from the lower power supply voltage Vss to the high power supply voltage Vii. The high power supply voltage Vii is supplied to peripheral circuits, such as the row address decoder, the word driver, and the dummy word driver, from outside the DRAM 100. The high power supply voltage Vii is decreased to generate stable cell power supply voltage ViiC.
A read operation performed by the DRAM 100 will now be discussed with reference to FIGS. 2A and 2B. FIG. 2A is a waveform chart of the DRAM 100 taken when cell information xe2x80x9c0xe2x80x9d is read from the memory cell 2a. FIG. 2B is a waveform chart of the DRAM 100 taken when cell information xe2x80x9c1xe2x80x9d is read from the memory cell 2a. 
The reading of cell information xe2x80x9c0xe2x80x9d will first be discussed. FIG. 2A shows voltage changes of the bit lines BL, /BL, the word line WL0, the dummy word line DWL1, and the latch enable signal LE. In this case, the voltage Vst at a storage node between the cell transistor Tr and a capacitor C1 of the memory cell 2a corresponds to the low power supply voltage Vss.
Prior to an operation for reading cell data, the bit lines BL, /BL are precharged to voltage ViiC/2 by a precharge circuit. The voltage of the dummy word line DWL0 is reset to the lower power supply voltage Vss.
Then, the word line WL0 is selected based on the row address signal and the voltage at the word line WL0 is increased from the low power supply voltage Vss to a step up voltage Vpp. In this state, when the voltage at the word line WL0 increases from the lower power supply voltage Vss by a threshold value Vthcell of the cell transistor Tr, cell information xe2x80x9c0xe2x80x9d is read to the bit line BL from the memory cell 2a and the voltage at the bit line BL decreases from ViiC/2.
In this state, when the dummy word line DWL0 is selected and the voltage at the dummy word line DWL0 is increased from the lower power supply voltage Vss to the high power supply voltage Vii, the charge of the dummy cell 5a increases the voltage at the bit line BL. The cell capacitor of the dummy cell 5a is set so that the increased voltage at the bit line BL is recognized as a low level by the sense amplifier 3. The cell capacitance of the dummy cell 5b is also set in the same manner. A differential voltage between the bit lines BL, /BL is amplified by the sense amplifier 3 that is activated by the latch enable signal LE. As a result, the voltage at the bit line BL changes to the lower power supply voltage Vss and cell information xe2x80x9c0xe2x80x9d is output from the bit line BL.
When cell information xe2x80x9c1xe2x80x9d is stored in the memory cell 2a, the voltage at the storage node between the cell transistor Tr and the capacitor C1 of the memory cell 2a corresponds to the cell power supply voltage ViiC.
In the state of FIG. 2B, the bit lines BL, /BL are precharged to the voltage ViiC/2 by the precharge circuit prior to the operation for reading the cell information. The dummy word lines DWL0, DWL1 are reset to the lower power supply voltage Vss.
Then, the word line WL0 is selected based on the row address signal and the voltage at the word line WL0 is increased from the low power supply voltage Vss to the step up voltage Vpp. In this state, when the voltage at the word line WL0 increases from the precharge voltage ViiC/2 by the threshold value Vthcell of the cell transistor Tr, cell information xe2x80x9c1xe2x80x9d is read to the bit line BL from the memory cell 2a and the voltage at the bit line BL increases from the precharge level (ViiC/2).
In this state, when the dummy word line DWL0 is selected and the voltage at the dummy word line DWL0 is increased from the lower power supply voltage Vss to the high power supply voltage Vii, the charge of the dummy cell 5a increases the voltage at the bit line BL. This increases the differential voltage between the bit lines BL, /BL and effectively increases the charge of the cell. Thus, the interval for refreshing the memory cells 2a, 2b is lengthened.
The differential voltage between the bit lines BL, /BL is amplified by the sense amplifier 3 that is activated by the latch enable signal LE. As a result, the voltage at the bit line BL shifts to the high power supply voltage ViiC and cell information xe2x80x9c1xe2x80x9d is output from the bit line BL.
The threshold value voltage Vthcell of the cell transistor Tr when reading cell information xe2x80x9c0xe2x80x9d differs in specifics from that of cell transistor Tr when reading cell information xe2x80x9c1xe2x80x9d. However, since the same operation is performed, the same reference character (Vthcell) is used.
The prior art method has the shortcomings discussed below.
(1) When the charge amount of the storage capacitor C1 associated with the cell information xe2x80x9c1xe2x80x9d decreases due to, for example, a leak, the cell storage voltage (voltage at the storage node) Vst decreases to a value less than or equal to the precharge voltage (ViiC/2). In this case, the cell information xe2x80x9c1xe2x80x9d cannot be read.
(2) The data holding time, or refresh cycle (tREF), of the memory cells 2a, 2b determines the current consumption during self-refreshing. When the refresh cycle tREF is short, the number of times self-refreshing is performed increases. This increases the self-refresh current.
(3) The time from word line activation to sense amplifier activation depends on the time required for the cell information xe2x80x9c1xe2x80x9d to be read from the memory cell 2a to the bit line BL. Further, the time from word line activation to sense amplifier activation is significantly affected by the threshold value Vthcell of the cell transistor Tr.
When the voltage at word line WL0 increases to the voltage required for reading the cell information (Viic/2+Vthcell), the cell information xe2x80x9c1xe2x80x9d is read to the bit line BL. Thus, if the rising edge of the word line voltage VWL has a gradual waveform, the time for reading data increases and the data read cycle time becomes longer. To prevent the rising edge waveform of the word line voltage VWL from becoming too gradual, the time constant (resistance and parasitic capacitance) of the word line must be decreased. To do so, an increase in the number of address decoders and word drivers required to drive the word line would enlarge the chip of the semiconductor memory device.
It is an object of the present invention to provide a semiconductor memory device that having improved characteristics for reading data stored thereon and a method for reading cell information from the inventive semiconductor memory device.
To achieve the above object, the present invention provides a semiconductor memory device including a memory cell for holding charge of first cell information or second cell information. The first cell information is associated with logic level xe2x80x9c0xe2x80x9d, and the second cell information is associated with logic level xe2x80x9c1xe2x80x9d. A word line is connected to the memory cell for supplying the memory cell with word line voltage. A bit line is connected to the memory cell for conveying the charge corresponding to the first or second cell information from the memory cell. A dummy cell is connected to the bit line for supplying the bit line with complementary charge. A dummy word line is connected to the dummy cell for supplying the dummy cell with dummy word line voltage. The first cell information is read based on the charge conveyed to the bit line from the memory cell when the word line is activated, and the second cell information is read based on the complementary charge supplied to the bit line from the dummy cell when the dummy word line is activated.
A further aspect of the present invention is a semiconductor memory device including a plurality of memory cells for storing first cell information or second cell information. The first cell information is associated with logic level xe2x80x9c0xe2x80x9d, and the second cell information is associated with logic level xe2x80x9c1xe2x80x9d. A plurality of word lines are connected to the memory cells for supplying the memory cells with word line voltage. A plurality of bit lines are connected to the memory cells for conveying charge corresponding to the first or second cell information from one of the memory cells. A plurality of dummy cells are connected to the bit lines for supplying an associated one of the bit lines with complementary charge. A plurality of dummy word lines are connected to the dummy cells for supplying the associated one of the dummy cells with dummy word line voltage. The first cell information is read based on the charge conveyed to the bit line associated with the memory cell connected to an activated one of the word lines, and the second cell information is read based on the complementary charge supplied to the bit line associated with the dummy cell connected to an activated one of the dummy word lines.
A further aspect of the present invention is a method for reading cell information from a semiconductor memory device. The semiconductor memory device includes a plurality of memory cells for holding charge corresponding to first cell information or second cell information. A plurality of pairs of bit lines are connected to the memory cells. Each pair of bit lines includes a bit line and an inverting bit line. The first cell information is associated with logic level xe2x80x9c0xe2x80x9d, and the second cell information is associated with logic level xe2x80x9c1xe2x80x9d. A plurality of word lines are connected to the memory cells for supplying the memory cells with word line voltage. A plurality of bit lines are connected to the memory cells for receiving charge corresponding to the first or second cell information from one of the memory cells. A plurality of dummy cells are connected to the pairs of bit lines for supplying an associated one of the pair of bit lines with complementary charge. A plurality of dummy word lines are connected to the dummy cells for supplying the associated one of the dummy cells with dummy word line voltage. A plurality of sense amplifiers are connected to the pairs of bit lines for amplifying the voltage between the associated one of the pairs of bit lines. The method includes a first step for activating at least one of the word lines, a second step for providing the first cell information to the bit line associated with the memory cell connected to the activated one of the word lines from the connected memory cell, a third step for activating at least one of the dummy word lines, a fourth step for supplying the complementary charge to the bit line associated with the dummy cell connected to the activated one of the dummy word lines from the connected dummy cell, and a fifth step for activating the sense amplifier connected to the bit line supplied with the complementary charge before the second cell information is read to the bit line.
A further aspect of the present invention is a method for reading cell information from a semiconductor memory device. The semiconductor memory device includes a plurality of memory cells for holding charge corresponding to first cell information or second cell information. A plurality of pairs of bit lines are connected to the memory cells. Each pair of bit lines includes a bit line and an inverting bit line. The first cell information is associated with logic level xe2x80x9c0xe2x80x9d, and the second cell information is associated with logic level xe2x80x9c1xe2x80x9d. A plurality of word lines are connected to the memory cells for supplying the memory cells with word line voltage. A plurality of bit lines are connected to the memory cells for receiving charge corresponding to the first or second cell information from one of the memory cells. A plurality of dummy cells are connected to the pairs of bit lines for supplying an associated one of the pair of bit lines with complementary charge. A plurality of dummy word lines are connected to the dummy cells for supplying the associated one of the dummy cells with dummy word line voltage. A plurality of sense amplifiers are connected to the pairs of bit lines for amplifying the voltage between the associated one of the pairs of bit lines. Each of the memory cells has a cell transistor threshold value voltage, a precharge voltage, a first sum voltage of the threshold value voltage and the precharge voltage, a write voltage for writing the second information to the memory cell, and a second sum voltage of the write voltage and the threshold value voltage. The method includes a first step for increasing voltage of at least one of the word lines from a reference voltage to a value greater than or equal to the threshold value voltage and less than the first sum voltage, a second step for providing the charge corresponding to the first cell information to the bit line associated with the memory cell connected to the at least one of the word lines, a third step for activating at least one of the dummy word lines, a fourth step for supplying the complementary charge to the bit line associated with the dummy cell connected to the activated one of the dummy word lines from the connected dummy cell, a fifth step for activating the sense amplifier connected to the bit line supplied with the complementary charge before the second cell information is read to the connected bit line from the memory cell, and a sixth step for increasing voltage at the at least one of the word lines to a value that is greater than or equal to the second sum voltage.